Mode of transfer in computer architecture

4 ATM protocol architecture 4.1 What is ATM protocol architecture? The asynchronous transfer mode (ATM) protocol architecture is designed to support the transfer of data with a range of guarantees for quality of service. The user data is divided into small, fixed-length packets, called cells, and transported over virtual connections. ATM operates over high data rate physical circuits, and the simple structure of ATM cells allows switching to be performed in hardware, which improves the speed and efficiency of ATM switches. Figure 24 shows the reference model for ATM. The first thing to notice is that, as well as layers, the model has planes. The functions for transferring user data are located in the user plane; the functions associated with the control of connections are located in the control plane; and the co-ordination functions associated with the layers and planes are located in the management planes. Figure 24 ATM reference model The three-dimensional representation of the ATM protocol architecture is intended to portray the relationship between the different types of protocol. The horizontal layers indicate the encapsulation of protocols through levels of abstraction as one layer is built on top of another, whereas the vertical planes indicate the functions that require co-ordination of the actions taken by different layers. An advantage of dividing the functions into control and user planes is that it introduces a degree of independence in the definition of the fu...

Data from Peripherals have to reach Memory so that the CPU can use it. Similarly, the processed output has to reach peripherals like printer, internet devices, DISK, etc. Thus, I/O data transfer is about how the three subsystems i.e. CPU, Memory and I/O Controller, are involved in achieving the data exchange with peripherals. The word Data Exchange means successful Data in/Data Out with necessary handshake and coordination. Data Exchange with a peripheral involves few steps and not straight forward as devices are mostly electromechanical and/or operate at a different speed than CPU and Memory. • The device to be initiated and checked for status whether it is ready for Data Exchange. • The data transfer has to happen at the acceptable capsule and speed of the device using the applicable protocol. • This may happen in more than one sequence, as necessitated. • If the device status is an Error status, it is to be suitably handled. I/O Controller's role is to ensure seamless data exchange by ensuring the following (Please refer to diagram 20.2) • Processor/Memory Communication • Device Communication • Control timing and Status processing – Coordination of the data traffic between CPU, Memory and Io devices • Data Buffering – To manage the data transfer speed mismatch • Error management ( Transmission errors are corrected other status errors are communicated) I/O Data Transfer Techniques CPU can be used very efficiently in Multitasking. Ideally, the involvement CPU in I/O data ...